DCC: различия между версиями

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(не показаны 4 промежуточные версии этого же участника)
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[[Категория:DCC]]
 
=DCC=
  
=DCC=
 
Заметки по ЖД моделям
  
Заметки по ЖД моделям
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<BR>
  
<BR>
 
<PRE>
  
<PRE>
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Instruction Bit Pattern
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Instruction Bit Pattern
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Direct CV addressing 0111 CCAA AAAA AAAA DDDD DDDD
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Direct CV addressing 0111 CCAA AAAA AAAA DDDD DDDD
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Direct CV addressing(bit) 0111 10AA AAAA AAAA 111K DBBB
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Direct CV addressing (bit) 0111 10AA AAAA AAAA 111K DBBB
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Page preset instruction 0111 1101 0000 0001
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Page preset instruction 0111 1101 0000 0001
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Address Only 0111 C000 0DDD DDDD
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Address Only 0111 C000 0DDD DDDD
 
Physical register addressing 0111 CRRR DDDD DDDD
  
Physical register addressing 0111 CRRR DDDD DDDD
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Paged CV addressing 0111 CRRR DDDD DDDD
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Paged CV addressing 0111 CRRR DDDD DDDD
 
</PRE>
  
</PRE>
   
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We can see that the instruction for Paged CV and Physical Register are the same. The RRR in these instructions refers to the register address. The value for the register address bits in Address Only is 000. This refers to CV#1 if the Paging Register is set to 1. CV#1 is the address. Therefore, Address Only is a special case of Paged CV.
  
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The bit pattern for the address of the Paging Register is 101. The bit pattern 0000 0001 sets it to Page 1. Therefore, the page preset instruction is a special case of Paged CV.
  
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⚫
So the addressing systems boil down to two main addressing methods - Direct CV and Paged CV. Let us look at the two again.
  
  +
We can see that the instruction for Paged CV and
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Physical Register are the same.
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<BR>
  +
  +
The RRR in these instructions refers to the register address. <BR>
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The value for the register address bits in Address Only is 000. <BR>
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This refers to CV#1 if the Paging Register is set to 1.
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CV#1 is the address.
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Therefore, Address Only is a special case of Paged CV.
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The bit pattern for the address of the Paging Register is 101.
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The bit pattern 0000 0001 sets it to Page 1.
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Therefore, the page preset instruction is a special case of Paged CV.
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<BR>
  ⚫
So the addressing systems boil down to two main addressing methods -
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Direct CV and Paged CV.
  +
Let us look at the two again.
  +
<PRE>
 
Instruction Bit Pattern
  
Instruction Bit Pattern
 
Direct CV addressing 0111 CCAA AAAA AAAA DDDD DDDD
  
Direct CV addressing 0111 CCAA AAAA AAAA DDDD DDDD
 
Paged CV addressing 0111 CRRR DDDD DDDD
  
Paged CV addressing 0111 CRRR DDDD DDDD
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</PRE>
 
There are some exceptions to this generalised view. For mobile decoders, in the physical register addressing mode, registers 7 and 8 refer to CV#7 and CV#8. In the Paged CV addressing mode, these registers are undefined. For accessory decoders, registers addressed in the physical register mode and paged CV mode are completely different.
  
There are some exceptions to this generalised view. For mobile decoders, in the physical register addressing mode, registers 7 and 8 refer to CV#7 and CV#8. In the Paged CV addressing mode, these registers are undefined. For accessory decoders, registers addressed in the physical register mode and paged CV mode are completely different.
 
Now let us look at packet sequences.
  
Now let us look at packet sequences.

Текущая версия на 09:19, 30 октября 2023

DCC

Заметки по ЖД моделям



Service Mode

Four addressing modes are described.

  • Address only
  • Physical Register
  • Paged CV
  • Direct CV

The two characteristics to study in the packets for service mode are packet bit patterns for individual packets and packet sequences for an operation.

Packet Bit Patterns

Here are the bit patterns for the various addressing modes.
Байт контроля ошибок опущен для краткости.
Note that some packets specified completely in the RP such as the page preset instruction contain the error byte but is not shown here. 

Instruction                        Bit Pattern
Direct CV addressing            0111 CCAA  AAAA AAAA  DDDD DDDD
Direct CV addressing (bit)      0111 10AA  AAAA AAAA  111K DBBB
Page preset instruction         0111 1101  0000 0001
Address Only                    0111 C000  0DDD DDDD
Physical register addressing	0111 CRRR  DDDD DDDD
Paged CV addressing	        0111 CRRR  DDDD DDDD



We can see that the instruction for Paged CV and Physical Register are the same.

The RRR in these instructions refers to the register address.
The value for the register address bits in Address Only is 000.
This refers to CV#1 if the Paging Register is set to 1. CV#1 is the address. Therefore, Address Only is a special case of Paged CV. The bit pattern for the address of the Paging Register is 101. The bit pattern 0000 0001 sets it to Page 1. 

Therefore, the page preset instruction is a special case of Paged CV.


So the addressing systems boil down to two main addressing methods - Direct CV and Paged CV. Let us look at the two again. 

Instruction	Bit Pattern
Direct CV addressing	0111 CCAA  AAAA AAAA  DDDD DDDD
Paged CV addressing	0111 CRRR  DDDD DDDD

There are some exceptions to this generalised view. For mobile decoders, in the physical register addressing mode, registers 7 and 8 refer to CV#7 and CV#8. In the Paged CV addressing mode, these registers are undefined. For accessory decoders, registers addressed in the physical register mode and paged CV mode are completely different. Now let us look at packet sequences. Packet Sequences A glance at the packet sequences for various service mode commands reveals a pattern. All packet sequences contain the same three elements. A few reset packets are sent The service mode command to accomplish a task is sent a few times. Let us call this command, to coin a term, the exec command. Optionally, the same exec command or reset packets are sent a few times. The number of times each packet has to be repeated is specified for each command. The repetition count for each command is listed below. Addressing Mode Command Type Reset Commands (min) Exec Commands (min) Reset or Exec Commands (min) Direct Mode Verify 3 5 - Direct Mode Write 3 5 6 Address Only Page Write 3 5 6 Address Only Register Verify 3 5 -

  • Address Only Register Write 3 5 10

Physical Register Page Write 3 5 6

  • Physical Register Register Verify 3 7 -

Physical Register Register Write 3 5 6 Paged CV Page Write 3 5 6 Paged CV Register Verify 3 5 - Paged CV Register Write 3 5 6

  • exceptions to the pattern

Both writes and verifys have the same pattern. The verify consists of 3 or more reset packets followed by 5 or more exec commands. The write consists of 3 or more reset packets, 5 or more exec commands and 6 exec or reset packets. There are two exceptions that make life difficult - writing to a register in address only and verify register in physical register addressing. Register Addresses - The 0 - 1 Issue Address calculations are complicated by the fact that binary values start from 0 but the designation numbers start from 1. Here are the instances where it happens. CV addresses in binary values in Direct CV addressing range from 0 to 1023 but actual CV number designations range from 1 to 1024. Physical register addresses range from 0 to 7 but register designations range from 1 to 8. There are two exceptions to this rule. One exception is Data Registers in Paged CV mode. The binary values range from 0 to 3 and so do the Data Register designations. Therefore, a value of 0 really means Data Register 0. The other exception is the contents of the Paging Register. This is where it gets confusing. The binary values range from 0 to 255. The page number designations range from 1 to 256. But the binary value 1 refers to Page 1. I assume the binary value 0 refers to Page 256 but I can't find any mention of it anywhere. Direct Addressing Direct Addressing allows access to any of the 1024 configuration variables.

The CC bits define the type of operation. A value of 01 is used for verify and a value of 11 is used for write operations. A value of 10 uses the bit mode of Direct Addressing described further on. The AA AAAA AAAA bits define one of the 1024 configuration variables. The DDDD DDDD bits define the data to be used in the operation. In the write operation, this value will be written into the CV specified. In the verify operation, the decoder would send an acknowledge if the data matches the current contents of the specified CV. In bit mode, these bits are further interpreted. Direct Addressing - Bit Mode The bit mode of Direct Addressing allows access to any single bit in any of the 1024 configuration variables.

The AA AAAA AAAA bits define one of the 1024 configuration variables. The BBB specify an individual bit within the specified CV. The D bit defines the data to be used in the operation. The K bit defines the operation - a 0 is used for a verify operation and 1 is used for a write operation. The bit mode for Direct Addressing is very powerful. It allows a single bit write and verify. It simplifies reading the contents of a CV. A CV is read by making repeated guesses at its contents and an acknowledge indicates a correct guess. Using the byte verify mode in any addressing mode, a worst case of 255 guesses are required. With the bit verify mode, a worst case of 8 guesses are required. In practice, for reliability, 16 guesses may be used which is still a lot faster than using byte mode verifys. Paged Addressing Paged Addressing allows access to all CVs using a two step process.

In Paged Addressing mode, the entire gamut of 1024 CVs is broken up into 256 pages of 4 CVs each. At any time, 1 of 8 registers can be accessed. Of these, the 6th register is used to specify 1 of 256 pages. The 1st to the 4th registers are then used to write into 1 of 4 CVs in that page. The configuration register is available as the 5th register. The RRR bits define 1 of 8 registers. The DDDD DDDD bits define the data used in this operation. The C bit defines the operation - a 0 is used for a verify operation and 1 is used for a write operation. To access a register, as a first step, the address of 1 of the 256 pages are placed in the Page Register. As a second step, 1 of the 4 registers are used to interact with a particular CV. Both steps are similar - they both write to a register and use the same basic command. Other Addressing Modes Both Address Only and Physical Register Addressing are similar to Paged CV. Both use Page 1 only. In Address Only mode, only CV1 in Page 1 is used. Both addressing modes involve setting the Page Register to Page 1. This is done using the Page Preset command. Therefore, the packet sequence is identical to Paged CV - a first step setting the Page Register to Page 1 and a second step writing to a particular register in that page. GPIO

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